Using an ICL7660 to feed -5VDC to 4116 DRAMs?

[Dave McGuire]

On Jul 2, 2008, at 1:48 PM, Ethan Dicks wrote:
>>   DRAM chips tend to draw spikes of current during refresh, as those
>> little capacitors get charged.
>
> Sure... I'm used to that with +5V-only chips like the 4164 and
> up, but I don't have any design experience with the multi-voltage
> parts, thus my caution.

   I've only worked with 41256s design-wise.  We used 8207 DRAM  
controllers, which were great in terms of functionality, but good  
heavens did we have problems with noisy power on those boards.  I  
never want to go through that again.  Those refresh spikes had such  
fast rise times (in ca. 1987 terms) that short, low-inductance paths  
to the bypass capacitors within the DRAM array turned out to be very  
important.

>>  If you have adequate low-impedance
>> bypassing to supply those short-term demands, things should be fine
>> with the 7660.  It's a fairly predictable and dependable chip.
>
> By low-impedance bypassing, you mean monolithic (not electrolytic)  
> caps,
> or do you mean something else?

   I just mean putting some decent bypassing electrically close to  
the board; presumably there are already a reasonable number of bypass  
capacitors in the DRAM array.  Steven Canning said the supply that's  
affected worst by refreshing is +12V...I didn't know that; if that's  
the case then you shouldn't have to worry all that much about  
bypassing -5V anyway.

>>> ... I wouldn't be able to get an order from Digikey for nearly 4
>>> months in any case.  I have to use what's on hand.
>>
>>   Good heavens, one would think you're in Antarctica or something.
>>
>>   Oh, wait.. ;)
>
> Yes... ;) indeed.

   :)

        -Dave

-- 
Dave McGuire
Port Charlotte, FL