CP-M Z80 home brew computer circuit board

[Allison]

>
>Subject: Re: CP-M Z80 home brew computer circuit board
>   From: "Eric Smith" <eric at brouhaha.com>
>   Date: Tue, 17 Jun 2008 11:53:23 -0700 (PDT)
>     To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
>
>Allison wrote:
>> As long as you can poll within the minimum read/write loop
>> time it's fairly easy. If not in the 8080/8085/z80 world you can use
>> processor ready line to do a stall-wait on DRQ to keep the loop in
>> sync and save some 22 T-states.
>
>I think you also need some logic to release the ready line if DRQ
>doesn't occur but an interrupt does, in order to handle error
>cases.

With the 765 you can OR the DRQ and the INT  lines for that.  Likely 
that works for 179x (and friends)as well.

>
>> I forget if 6502 has a ready wait line.
>
>It does, but on the NMOS parts it only can stall read cycles, not
>writes.  (In the early-to-mid 1970s, ROMs and EPROMs were much slower
>than typical SRAMs, so the designers apparently didn't think there
>was any need to stall on writes.)

I know so well Eproms were slow.

>
>For the controller I designed, I dealt with that by having a special
>address that could be read that only waited for DRQ, at an address
>in the page below the FDC's data register.  By itself, that wasn't
>sufficient to get to 8" MFM on a 1 MHz 6502.  However, by taking
>advantage of the spurious read that occurs on indexed write
>instructions when there is a page crossing, I got the read of the
>special polling adress and the write of the data in a single
>instruction.  That gets it down to 16 cycles, which meets the
>nominal rate but isn't actually good enough.  By unrolling the
>loop, though, it drops to 13 cycles per byte, which meets all
>the requirements:

Thats pretty crufty. 

>             LDA  (DPTR),Y       ; get data byte from buffer
>             STA  FDC_SPCL,X     ; reads poll location, which stalls,
>                                 ;    then writes data
>             INY
>
>The unrolled loop requires 6 bytes of code per byte transferred, which
>is 1536 bytes for a 256-byte sector.  Not great, but it did fit in a
>2716 EPROM.  I used two 2716s, one containing the read loop and one
>containing the write loop, both mapped into the same address space
>and selected by writing to another port address.  The rest of the
>FDC driver fit in the remaining space of the two EPROMs.
>
>I didn't anticipate that they would "fix" the RDY behavior and the
>spurious read on the 65C02, so the same code wouldn't work on that.
>However, the fix was simply to replace the indexed STA with an
>absolute STA.

Don't you love it when that happens.  In the 8080/8085/z80 world that
kind of processor tweek was less common by vendors as absolute 
compatability with intel (the compatition) was desireable.

However having done that far to many times for many different cpus
I'll pass on further floppy integration.  CF or even IDE gets me 
to enough space and decent speed with far less pain.

Allison

>Eric