Z80 instruction fetch mechanism

[Jules Richardson]

Someone asked this over on the Sinclair group a short while ago, but I 
suddenly thought that someone here might know...

Basically they were wondering what the internals of the Z80's instruction 
fetch were, given that some instructions are multiple bytes in length, but 
there's only a single-byte instruction register.

I theorised that control in the Z80 is all just a state machine, so multiple 
instruction bytes presumably advance things to a new state (and what's left in 
the IR during execution is just one byte from a multi-byte instruction) - but 
it sounds like the OP was wondering if anyone knew the exact mechanism 
(basically, has the design of the state machine ever been documented anywhere).

(Given that I'm on a 'homebrew CPU' trip right now, I'm rather curious, too :-)

Quite possibly this level of detail's never been made publicly available, but 
I figure someone here may have had close involvement with Zilog and know more. 
Online resources cover the overall internal architecture, but just 'black box' 
the control logic section (including the IR).

cheers

Jules