(Resending) Re: Further 11/40 unibus questions...

Josh Dersch derschjo at mail.msu.edu
Tue Jun 9 22:53:04 CDT 2009


Resending this, as it seems to have not made it to the list for whatever 
reason.  (Sorry if this ends up in people's mailboxes twice...)

Tony Duell wrote:
>>> Then I'd look at all the Unibus signals both with the terminator out 
>>> (they will still be terminated by the resistors at at the CPU end -- 
>>> IIRC on an 11/40 these are on the Unibus jumper between the CPU and 
>>> first expansion backplane) and with it fitted. I would guess 
>>> something is changing state, let's find out what.
>>>         
>> I will start looking at this tonight (assuming I have the time 
>> tonight :)).  Thanks.
>>     
>
> OK, let us know how you get on :-)
>
> -tony
>   

Ok, finally stopped being distracted by other shiny objects for long 
enough to do some more fiddling with the 11/40.

And of course, instead of hooking up the logic analyzer, I decided to 
play around with the Console SLU/LTC board.  Because I evidently don't 
follow suggestions well.
But this has a good ending, sort of.  Maybe.

So the SLU was unresponsive no matter what I did.  Tried it at 9600 
baud, no go.  Dialed it down to 300, no dice.  Checked the continuity of 
the dip switches, of which there are approximately 500.  No problems 
there.  Checked, and double-checked the wiring on the serial cable I 
built.  No go.   Stole the cable from my 8/e... still no good.

So I moved it out of the 9th slot on the processor backplane and into 
the first slot on Unibus backplane.  (And put a grant card in the 9th 
slot...) And hey, it works.  Toggled in a short "echo" program and what 
I type on the terminal keyboard is echoed back, at a blistering 300 baud.

So... clearly there's something wrong with the SPC slot on the processor 
backplane.  A couple more questions:

1) Is the NPG grant on the unibus slot on the processor backplane (slot 
9) supposed to be connected to the NPG grants on the Unibus expansion?  
That is -- right now if I set my DMM to continuity mode and put one 
probe on CA1 on the first slot of the unibus expansion, and the other on 
CB1 on the last slot of the unibus expansion, since all NPG grant 
jumpers are in place, the DMM shows the circuit as closed.  This is as 
I'd expect.  However, if I move the probe from CA1 on the first slot of 
the expansion to CA1 on slot 9 of the processor backplane, the circuit 
is then open.  I'm guessing this is not correct.  (There is currently an 
NPG jumper installed on slot 9.)

2) Where is the +15V to the processor backplane supposed to be 
connected?  (I suspect this may be the reason the SLU won't function in 
slot 9...).  Right now it's plugged into pin CV1 on slot 9 (if I'm 
reading the Unibus pin chart right :)) but the docs I have found say 
this should be ACLO_L...


Thanks as always...
Josh



More information about the cctech mailing list