fpga pdp's; [was Re: ...arrogance [was RE: UNIX V7] ]

Brad Parker brad at heeltoe.com
Fri Jun 12 19:36:20 CDT 2009

Eric Smith wrote:
> Brad Parker wrote:
>> I did a "direct decode" pdp-11 in verilog recently just to see how 
>> big it would be (and because I was frustrated with the pop-11 
>> project).  It fits nicely & boots RT11 at 50mhz.
> At that speed, surely it hasn't finished booting RT11 yet!
sorry, I don't get the joke.  clock is 50mhz, or 20ns; each state is one 
clock and on average
an instruction is 3 states.  I calculated 10mips.  it seems to boot much 
faster than my 11/44 :-)

what did I miss?


More information about the cctech mailing list