6800/6820 Address decoding help...

Tony Duell ard at p850ug1.demon.co.uk
Sat Mar 7 13:20:41 CST 2009

> ard at p850ug1.demon.co.uk wrote:
> >
> > It sounds like what you need is a 6820 PIA data sheet (a 6821 one would do
> > as well). This shouldn't be hard to find.
> >   
> These are actually in Vol. 2 of the service manual, at the back :).



> > There seem to be some useful tables at the start of the second volume of the
> > service manual saying what each of the port lines is linked to. Given that, 
> >   
> <slaps forehead>  I didn't even see that section of the service 
> manual... just jumped straight to the schematics.  More fool me... this 
> is quite helpful.

I think the expression is 'Read The FIne Manual' (and this is a fine 
manual from what I've seen).

If you want to work out the addressing from first principles, you need to 
look at the CSn (Chip Select) inputs to the PIAs. IIRC there are 3 of 
these on a 6820, CS0 and CS1 have to be high (logic 1) and CS2/ has to be 
low (logic 0) to select the PIA. Any other combination  oprevents the CPU 
from accessing that PIA.

>From what I rememebr of the scheamtics, CS0 and CS1 are connected to 
buffered address lines, CS2/ comes from an active-low output of an 
addresss decoder circuit. I think (based on the CS0 and CS1 wiring) that 
the decoding is not 'complete'. Each PIA may appear at several addresses, 
and there are some addresses that would actually select 2 PIAs 
simultaneously. A very bad idea if you're reading from the PIA (both of 
the selected PIAs would try to drive the data bus at the same time), but 
proably OK for writing. I have no idea if Tektronix ever did this, but it 
would appear you could write the same value to equivalent registers in 2 
PIAs at the same time. 

Something to think about if your simulator appears to be writing to PIAs 
and non-standard addresses.

> I think I've got most of it worked out now... just not sure how to work 
> out where the control lines (CA1/2, CB1/2) fit into this whole thing.

They're controlled via each port's control register. IIRC the control 
inputs generate interrupts,  I've not looked to see how the interrupt 
outputs of the PIAs are wired in the 4051.


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