cctech Digest, Vol 78, Issue 3
bfranchuk at jetnet.ab.ca
Sun Feb 7 22:11:48 CST 2010
Dave McGuire wrote:
>> See: CPLD design. This current design is CPLD/2901 bitslice design.
>> The ALU is 12 bits, double clocked to give a 24 bit CPU on a 6800/6502
>> style memory cycle.One CPLD is for high speed decoding and the other
>> for the MAR and MBR data paths. A 8 bit refresh counter is for DRAM's.
>> A 2.5 MHZ (top speed)clock gives a 800 ns memory cycle. 3 2901's make
>> up the data path.
> That sounds like fun.
> Had you ever thought about making boards for these to sell to people?
> I'd want a couple, I'll bet some other people would buy them too...they
> sound like fun to hack on.
I plan to make up some PCB's for my local use, when I get off my butt.
Right now I am taking a short break, since I am not sure just what the
rest of the design will be like. Most likely similar to the Mark 8
micro-computer with a 50 pin ribbon cable buss and PC floppy drive
connectors for power. It looks like about 6 boards.
A) clock/front panel
C) 128 kb static ram
D) 128 kb static ram/EEPROM
E) Uart/IDE interface
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