yet another pdp-8 in a fpga, but this time running tss/8

Philipp Hachtmann hachti at
Tue Jun 8 10:13:06 CDT 2010

>> The flip-flops may be driven by the external clock input, but often this
>> is not the case. Almost all modern FPGAs contain either PLL or DLL
>> blocks that can be used to synthesize other clock frequencies from the
>> external input.
> Right. I've used Xilinx's DCMs before.  They are pretty simple and 
> provide a wide range of output frequencies.  My eval board has a single 
> SMA connector on it for high frequency connections.  The forty free I/O 
> pins use a hirose FX2 connector, not sure what the highest frequency is 
> available there.  I wouldn't think even to 100mhz?
Xilinx Spartan-3e board? Nice toy! A pdp8 fits several times...

>> On the FPGA eval boards with a 50 MHz oscillator, I
>> routinely run the flip-flops of my designs at frequencies up to 200 MHz.
> My real point to the original poster was that they don't run at ghz 
> speeds.  Or even close.
200MHz is quite fast - at least on a Spartan-3... Or you have a very 
very simple design. Could look different on a newer Virtex device.

> Despite looking at the datasheet this morning, I have no idea what the 
> maximum frequency of my Spartan-3E XC3S500E-4FG320C, speed grade -4 is. 
>  I've fed the coregen DDR controller at 100mhz before, but never used 
> anything faster.
I assume that you could reach about 150 MHz with very good design or 
very limited functionality. I have not yet fully understood the timing 
constraints you pass to the Xilinx tools. It could speed things up if 
you exclude some unimportant paths like wires going to LEDs on a pdp8 
implementation. I assume that IO cells in timing paths add a lot bigger 
delay than simple logic...

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