yet another pdp-11 in fgpa
quapla at xs4all.nl
Tue Jun 22 02:34:06 CDT 2010
> Johnny Billquist wrote:
>> "Walter F.J. Mueller" <W.F.J.Mueller at gsi.de> wrote:
>>> The reason why I picked a 11/70 and not a J11 as target is because my
>>> goal is a 11/74. I've implemented the IIST already and tested against
>>> the IIST Diagnostic I could find in XXDP (riiab0). A dual core will
>>> fit into a single xc3s1200e of the NEXYS2 board. The work needed is
>>> quite clear and doable (changes on cache, mmu, and cpu core for asrb).
>>> However, I've no plans to implement the CIS, so it will always be a
>>> subset of a 11/74. But for sure fun to do and run.
>> You do know that the J11 is already designed for mP usage, except that
>> DECs testing of that was even more secret than the 11/74?
>> The 11/74 definitely don't need CIS though. I don't think any
>> prototype 11/74 even had it. It was planned for the next generation of
>> the machine, that never got built. Anyway, it was to be an option for
>> the CPU as far as I know. Just as FPP.
> Here's a front panel from a 'real 11/74', the uniprocessor one with
> CIS: http://www.ak6dn.com/stuff/1174.jpg
> Note the CIS uADDRS and other CIS status lights selectable on the rotary
> switch on the right.
> The marketing dinks appropriated the 11/74 moniker for the wanna-be
> 11/70mp program because '11/74' sounded better for a 4 way MP system.
Ahh, yes marketing.....
> After the 11/74 CIS COBOL benchmarks came in, the native PDP-11 CIS
> implementation on the 11/74 blew the 11/780 benchmarks away. DEC
> marketing did not like this; it made selling business customers the just
> released 11/780 more difficult. The decision was made to kill the 11/74
> CIS option the day we released it to manufacturing in favor of the new
> VAX system.
> Johnny is right, the 11/74 option was a multiboard set (just like the
> FPP option) that could be plugged into the new 11/74 backplane (which
> was an 11/70 backplane with all the CPU and FPP slots pushed down by
> four to make room for the CIS option in the first slots).
How was this achived? By reducing the Massbus card space by 4 boards
so 3 interface sections were available? Or by redesigning the processor
in such a way that there were less boards needed?
> I wish I had saved more documentation (print sets, microcode listings,
> etc) but to my knowledge none of this survives for the 11/74 CIS. Only
> my front plex panel which I took as a souvenir.
> I was one of the three engineers who wrote the microcode for the CIS
> option subsystem (total of 4K words of 96bit wide horizontal microcode).
>> IIST is needed for RSX to be happy (the only OS that supports the
>> 11/74), and you also need to implement parts of the memory bus
>> behaviour with interlocking. You can ignore the MK11 box CSRs, even
>> though it will look a little funny, but you do need separate DL11s for
>> each CPU core, along with the rest of the I/O bus, or else things will
>> probably not work. The 11/74 is a shared memory machine, but not
>> shared I/O bus.
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