Ones' complement adder/subtractor

[Chuck Guzis]

I've seen a little discussion of ones'complement (or "compliment if 
you're a recent graduate of the US university system) on the EDA 
fora, with no satisfactory resolution of the end-around carry 
stability issue.

Given that almost every CPU that I've seen since 1980 has operated in 
two's complement, I submit that this qualifies as a "classic" 
discussion.

I can't seem to derive a stable expression (Verilog) for adding two 
numbers, A and B,in ones' complement without computing A+B and A+B+1 
as a two's complement adder and then selecting one or the other 
result depending on the carry-out.  This seems to me to be a huge 
waste of logic.

Has anyone in their FPGA simulations ever run into this one and come 
up with a clever solution?

Just curious,
Chuck