Ones' complement adder/subtractor

Chuck Guzis cclist at sydex.com
Fri Oct 1 21:16:32 CDT 2010


On 1 Oct 2010 at 18:37, William Maddox wrote:

> I am not sure exactly what you mean by a "stable expression", but I
> presume that your difficulty is in coming up with a purely
> combinational formulation of the end-around carry, suitable for
> execution in a single cycle, that seems suitably economical in logic.

Exactly--if you take a simple adder and send the carry-out to the 
carry-in, you wind up with a race condition.  You could clock the 
circuit and run a second addition/increment based on the presence of 
carry-out, but then you've got a synchronous adder with a delay of 
either one or two clocks.  If you're after an adder that operates 
either asynchronously or synchronously in a specific number of 
clocks, you have to settle for 2 clocks--one clock seems not to be 
possible.

I've been doing some research since my post and patent 4,298,952 uses 
ancillary logic to generate a carry-lookahead signal independent of 
the adder.  I'm not sure if this accomplishes much.

The other patent I can find on the subject is essentially the scheme 
that I first described--compute two sums and then select the 
appropriate one--is 6,343,306, published in (surprisingly) 2002 and 
assigned to Sun.

Another is 4,099,248, from 1978, that describes a substractive adder, 
such as used in the older CDC gear (minimizes the problem of negative 
zero), but implemented with 10K ECL logic blocks.

This one's been scratching at my brain for some time and I wondered 
if anyone had any background on it.

Thanks,
Chuck










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