Ones' complement adder/subtractor
eric at brouhaha.com
Sat Oct 2 11:50:31 CDT 2010
On 10/01/2010 07:16 PM, Chuck Guzis wrote:
> patent 4,298,952 uses
> ancillary logic to generate a carry-lookahead signal independent of
> the adder. I'm not sure if this accomplishes much.
It does exactly what you've asked for. The point of it is that if
you're using off-the shelf parts, or off-the-shelf standard cells in an
ASIC, you already can get adders with the carry lookahead logic. In an
FPGA you don't, so the dual-adder design you described (and Sun
patented) will generally have lower resource utilization and be faster.
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