Ones' complement adder/subtractor

[Dan Roganti]

On Fri, Oct 1, 2010 at 4:08 PM, Chuck Guzis <cclist at sydex.com> wrote:

>
>
> I can't seem to derive a stable expression (Verilog) for adding two
> numbers, A and B,in ones' complement without computing A+B and A+B+1
> as a two's complement adder and then selecting one or the other
> result depending on the carry-out.  This seems to me to be a huge
> waste of logic.
>
>
>
that's been the problem with FPGA synthesis all along, they've never been
more than average at best

as they always say, when in doubt, instantiate  !  ;)

=Dan
--http://www.vintagecomputer.net/ragooman/