Ones' complement adder/subtractor

Chuck Guzis cclist at sydex.com
Sat Oct 2 13:04:08 CDT 2010


On 2 Oct 2010 at 9:50, Eric Smith wrote:

> It does exactly what you've asked for.  The point of it is that if
> you're using off-the shelf parts, or off-the-shelf standard cells in
> an ASIC, you already can get adders with the carry lookahead logic. 
> In an FPGA you don't, so the dual-adder design you described (and Sun
> patented) will generally have lower resource utilization and be
> faster.

Why the Sun patent doesn't qualify as "prior art" is beyond me.  But 
the patent system is "grant first, litigate later", so it figures.

I'll probably end up doing a 2-stage/2-clock adder-followed-by-
incrementer.  At least it's straightforward.

Thanks,
Chuck




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