Ones' complement adder/subtractor

dwight elvey dkelvey at hotmail.com
Sat Oct 2 18:49:42 CDT 2010


> From: eric at brouhaha.com
> 
> On 10/01/2010 07:16 PM, Chuck Guzis wrote:
> > patent 4,298,952 uses
> > ancillary logic to generate a carry-lookahead signal independent of
> > the adder. I'm not sure if this accomplishes much.
> 
> It does exactly what you've asked for. The point of it is that if 
> you're using off-the shelf parts, or off-the-shelf standard cells in an 
> ASIC, you already can get adders with the carry lookahead logic. In an 
> FPGA you don't, so the dual-adder design you described (and Sun 
> patented) will generally have lower resource utilization and be faster.
> 
> Eric
> 

Hi
 Another possible is to put an incrementor on the output. This
is a simpler circuit than a full adder.
Dwight
  		 	   		  


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