hardware multiply/divide functionality in CPUs (6809)

[Mark Tapley]

At 23:56 -0600 3/7/11, Jules wrote:
>Yes, that seems to be the 'famous' one that gets mentioned everywhere. It
>seems it was of the shift-add variety. Anyone recall if it would work with
>signed integers? (I'm just trying to work out how the math works for signed
>multiplies at the moment)

	I have a scanned .pdf of the 6809 programmer's manual here, 
happy to send out if anyone wants it, but it's 12.8 MBytes. (I got it 
from the freescale website, since reorganized; it's online at 
http://www.maddes.net/m6809pm/ .)

	It says the MUL instruction A x B -> D (unsigned) takes 11 
MPU cycles.  ADD instructions take a minimum of 2 cycles, as do shift 
(roll, etc) instructions. So I think maybe there must have been some 
silicon (vs. microcode) involved in the multiply? I don't see how the 
shift-add sequence could be done in only 11 cycles.

	MUL is unsigned arithmetic only.
-- 
						- Mark     210-379-4635
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