hardware multiply/divide functionality in CPUs (6809)

[Jules Richardson]

Mark Tapley wrote:
> At 23:56 -0600 3/7/11, Jules wrote:
>> Yes, that seems to be the 'famous' one that gets mentioned everywhere. It
>> seems it was of the shift-add variety. Anyone recall if it would work 
>> with
>> signed integers? (I'm just trying to work out how the math works for 
>> signed
>> multiplies at the moment)
> 
>     I have a scanned .pdf of the 6809 programmer's manual here, happy to 
> send out if anyone wants it, but it's 12.8 MBytes. (I got it from the 
> freescale website, since reorganized; it's online at 
> http://www.maddes.net/m6809pm/ .)
> 
>     It says the MUL instruction A x B -> D (unsigned) takes 11 MPU 
> cycles.  ADD instructions take a minimum of 2 cycles, as do shift (roll, 
> etc) instructions. So I think maybe there must have been some silicon 
> (vs. microcode) involved in the multiply? I don't see how the shift-add 
> sequence could be done in only 11 cycles.

I see what you mean - I wonder if the actual add only takes one cycle, but 
there's an additional 1-cycle overhead (none of the instructions seem to be 
less than 2 cycles) which doesn't scale to 8 shifts/adds needed for an 
8-bit multiply? That would make sense, I think - 8 cycles of shifts/adds, 
standard 1 cycle overhead, and 2 more cycles eaten up doing housekeeping 
"stuff".

cheers

Jules