hardware multiply/divide functionality in CPUs

[Christian Corti]

On Mon, 7 Mar 2011, Tony Duell wrote:
>> * mainframe, mini, micro; I'm not picky. I'm more interested in building up a
>> picture of how widespread hardware support was, and the various approaches
>> that designers used.
>
> What do you mean by 'hardware' multiply and divide? A number of machines,
> I suspect the 6809 is amongst them, had no particualrl hardware for
> multiply or divide, but they did have multiply and maybe divide
> instrucitons in the instruction setc. These instrucitons were implemented
> by microcode using the normal registers and ALU. Does that count?

I'd say no, microcode is software. Looking at our own collection, the 
LGP-30 implements multiply and divide in hardware, as well as e.g. the 
Diehl Combitron (designed around 1965). The last one is particularly 
interesting as its word length is 55 bits but the number of significant 
result bits is variable, depending on the given number of R delay line 
cycles. Multiplication is shift+add, division is shift and substract/add 
(depending on the sign of the previous remainder). This all is done in HW 
with just a hand full of flip-flops (in the whole processor!).

Christian