Cyber ECL Wiring
bpettitx at comcast.net
Fri Nov 28 00:35:45 CST 2014
Eric Smith wrote:
"Another approach is to use single-ended on a module, but only differential
between modules. To do it properly, the differential signals between
modules need to be twisted pairs."
You are correct. Eric, have you seen a Cyber 170 chassis? There is no back plane. Every signal uses twisted pair wire wrap from module to module. It was horrible to build, wire mats inches thick. We used to allow field engineers 10 minutes per signal line for engineering change orders.
Provided, the line did not need to be tuned. Tuning was done by changing wire length. It was not elegant by later standards but was very very fast for the era. One of the downsides to using differential wiring throughout the system was the manufacturing time measured in months. Of course, they sold for millions or tens of millions of dollars so it was worth this approach.
At the time, early 1970's, there was not a lot LSI available in ECL. So most of the Cyber series, and early Crays used SSI. Chip count was never as important as speed. The one MSI that I remember being critical was the 10181, an ALU chip. To use it and keep signal lengths short, the arithemetic chassis was laid out with the ALUs in the middle and the registers around them in a circle. The carry tree was at the center of design. Internally, word size was a bastard mix of 60 and 64 bits.
The higher performance models were a mixture of discrete modules from the 7600 and ECL modules from the Cyber 173. It's hard to visualise with today's technology. The multiply unit took an entire chassis! Memory took multiple chassis.
All I/O cables and interchassis cables were differential tuned cables. All I/O had to use the same length cables.
As Chuck mentioned, 400 Hz MGs provided the power. It was distributed to the chassis where the diodes were mounted in alunimum bars, cooled by freon. If you get a chance sometime, look at the Cray-1. The part where you sit is all power components. The circular logic chassis was primarily to keep wire length short.
Seymour tried to build it using an absolute minimum of chip types, only two for much of the logic. He felt that MSI and LSI stole speed from his design.
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