11/23 clock issue

Brent Hilpert hilpert at cs.ubc.ca
Sun Feb 8 21:12:10 CST 2015

On 2015-Feb-08, at 3:20 AM, Holm Tiffe wrote:
> Brent Hilpert wrote:
>> On 2015-Feb-07, at 11:20 AM, Holm Tiffe wrote:
>>> Pete Turnbull wrote:
>>>> On 06/02/2015 07:44, Holm Tiffe wrote:
>>>>> You don't ned no pullup for +5. All open TTL inputs are reading High w/o
>>>>> any pullup.
>>>> Yeah.  So someone at Commodore thought when they designed one version of 
>>>> the PET.  We had a few that erratically misbehaved.  It turned out that 
>>>> one input on a 74LS00 (I think it was) was floating, and switching noise 
>>>> made it erratic.  Floating inputs place the internal circuitry in an 
>>>> intermediate state, can cause increased current draw, typically slow the 
>>>> device down by increasing switching times, and can cause misbehaviour.
>>>> TTL is supposed to have a 1K pullup (to limit possible transients); 
>>>> LSTTL can be directly connected to Vcc.
>>>> -- 
>>>> Pete
>>>> Pete Turnbull
>>> Yes Pete, not all People over here are totally braindead.
>>> I've told him that he can leave out the +5V Connection for testing
>>> purposes, for nothing other.
>> No you didn't. While the context of the discussion is testing and that may have been your intention, your comment specified no such qualification, and as such at best left it ambiguous/unclear.
>> Pete's comment was valid clarification and additional information (although I could have minor quibbles with some of the technical phrasing).
> You are simply wrong.

>  I'm answered in a thread reagarding a fault in a
> clock circuit of an PDP11 Processor Board, not in a discussion regarding
> the design of a new board with TTL cicuits.

Pete clarified your potentially misleading statement. He wasn't "pissing on your feet".

Sometimes Holm, attempts at redemption just result in digging yourself in deeper.

> Besides of that Petes sentence "TTL is supposed to have a 1K pullup (to
> limit possible transients); LSTTL can be directly connected to Vcc." above
> is plain wrong too.
> Direct me to a datasheet containing this please.

You are wrong, Pete is correct.

This was discussed on the list in 2014 October.
Quoting myself quoting Fairchild and TI databooks:

		This is addressed in, for example, the characteristics and design treatises at the beginning of Fairchild TTL databooks.
		(from the 1978 version):

			"For a permanent high signal, unused inputs can be tied to Vcc.

			A current limiting resistor, in the range of 1K to 5K, is recommended for emitter-type inputs since these break down
			at some unspecified voltage over 5.5V and power supply misadjustment or malfunction can cause damage unless
			current is limited.

			.. diode-type LS-TTL inputs have breakdown voltages above 15V and thus protective resistors are not normally required."


		Here's a quote from TI, mentioning the same 5.5V extreme as Fairchild, but not providing the explanation:

		From "TTL Integrated Circuits Catalog from Texas Instruments" / 1 Aug 1969:

				"Unused inputs of AND and NAND gates and unused preset and clear inputs of flip-flops:

					Tie directly to +Vcc where Vcc is guaranteed to *always* be <= 5.5V;   (emphasis TI's)
					Tie to Vcc through resistor >= 1Kohms. Several unused inputs may be tied to one resistor;
					Tie to unused input of same gate if maximum fan-out of driving device will not be exceeded;
					Tie to unused gate output where unused gate input is grounded.

Would you like photos of the appropriate pages?
Certified copies couriered on overnight express to your front door?

More information about the cctech mailing list