Reverse engineering vintage PCBs
alan at alanlee.org
Thu Jan 8 20:35:53 CST 2015
I appreciate all the input from folks. With 3600 though holes and at
least 4 layers, I'm afraid I will make mistakes using any manual method
like ohm tracing without a check or balance. With so many permutations
and little personal knowledge about the WE chipset, I'm sure I will miss
an occasional trace that shoots to the other side of the board. I'm also
worried that I might generate a false positive keeping most of the
components wired. Something akin to body diodes (yes I know this isn't
CMOS). Here is a wiki photo of the board for reference:
As I said the board isn't very useful in it's current state. So I will
start by dropping the components off and removing the solder mask with a
sanding pen. I've had good luck in the past photo transferring a scanned
image of the board into eCAD with contrast enhancement. That will at
least get me the top and bottom layers with good accuracy. If manual
tracing of inner layers proves to laborious, I'll revisit automated
To add to Chuck's question, I've thought about that too. With the open
nature of KiCAD and Eagle file formats, it should be straight forward to
generate a schematic from a text netlist (or even IPC-D-356). Especially
since both contain definitions for the referenced schematic symbols. eg
you can synth a 'generic' DIP-16-U<n> symbol to go with that yet to be
defined part in any library.
On 2015-01-08 03:53, Eric Smith wrote:
> On Wed, Jan 7, 2015 at 10:57 PM, tony duell <ard at p850ug1.demon.co.uk> wrote:
>> and a lot of (pleasant) time.
> I don't find it all that pleasant, but at least there's a sense of
> when I'm done.
>> Anyway, when you have finished, feel free to make the schematic unreadable by redrawing it in a CAD system.
> I just did that for the PSE Pacer CPU card. Is it unreadable?
> http://www.brouhaha.com/~eric/retrocomputing/pse/pacer/pac-mp-001.pdf 
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