Reproducing old machines with newer technology (Re: PDP-12 at the RICM)

Dave G4UGM dave.g4ugm at
Tue Jul 14 09:10:31 CDT 2015

> -----Original Message-----
> From: cctalk [mailto:cctalk-bounces at] On Behalf Of ANDY HOLT
> Sent: 14 July 2015 10:20
> To: General Discussion: On-Topic and Off-Topic Posts
> Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
> the RICM)
> >>>>
> ----- Original Message -----
> From: "Dave G4UGM" <dave.g4ugm at>
> To: "General Discussion: On-Topic and Off-Topic Posts"
> <cctalk at>
> Sent: Tuesday, 14 July, 2015 8:58:09 AM
> Subject: RE: Reproducing old machines with newer technology (Re: PDP-12 at
> the RICM) ...
> My next project is likely to be the Ferranti Pegasus which is several orders of
> magnitude more complex than the Baby and will need a proper plan.
> <<<<
> "There may be troubles ahead" …
> I had plans for doing something similar for the ICT1905 (FP6000) and
> discovered two catches in translating the logic diagrams:
> FPGAs are designed around the modern concept of a single clock that is widely
> distributed and having flipflop control by gating the input signals whereas early
> Ferranti machines (1900, at least pre "A" series, Atlas*, and presumably
> Pegasus) used "strobes" which are hard and inefficient to do in a FPGA.

Actually the Pegasus "should" be relatively easy to implement in FPGA. It is all locked to 333Khz clock track derived from the drum. As all storage elements are delay lines which also run at the same speed as the drum, so you can transfer data between the two without using buffers almost everything is tightly coupled to the 333Khz clock. It was also one of the first machines to use standard replicable modules. According to Simon Lavington's book (which I don't trust 100%)  there are 20 types of package in a  basic Pegasus I, and you need 444 to build the machine. Out of these 314 are used to build the CPU but there are only 5 types of standard module.  So in practice its built a bit like a large PDP/8S but with Valves.

Charles Owen who Lavington credits with coming up with the Module Concept went to work for IBM in 1956 and was later made an IBM fellow.

> Maybe less likely to be the case in the Pegasus is the widespread use of "wired-
> or" which can be hard to recognise in the logic diagrams (and, again, requires
> translating into "real" gates in an FPGA) Obviously a register transfer model
> wouldn't have those problems compared to a gate-level model and would be
> considerably simpler to implement but then risks losing some of the (possibly
> undocumented) edge cases.

It has germanium diodes so few wired OR's as far as I know.

> * Atlas would, presumably, be even trickier due to the use of asynchronous
> logic.

Altas would be great fun. I suspect you could do it by using multiple independent clocks and complex handshaking...

> Good luck, should be an "interesting" exercise.
> Andy


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