Reproducing old machines with newer technology (Re: PDP-12 at the RICM)
bfranchuk at jetnet.ab.ca
Tue Jul 14 11:55:45 CDT 2015
On 7/14/2015 10:29 AM, Paul Koning wrote:
>> On Jul 14, 2015, at 12:23 PM, ben <bfranchuk at jetnet.ab.ca> wrote:
>> On 7/13/2015 10:02 AM, Paul Koning wrote:
>>> A different approach is to reproduce the actual logic design.
>>> FPGAs can be fed gate level models, though that’s not the most
>>> common practice as I understand it. But if you have access to
>>> that level of original design data, the result can be quite
>> The big assumption here, is the software will NOT change the logic
>> model and the details are vender specific. Altera software is BAD
>> for doing this.
> So now I know two reasons not to use AHDL. :-)
It is more the case, of what you don't know can't hurt you. This is a
back end of the compiler problem. With FPGA logic changing every 6
months, you have less standard logic blocks.
> Yes, it does require that the synthesis software doesn’t have major
> bugs. And of course, the model has to be sufficiently constrained
> that it steers the synthesis correctly.
With AHDL I know what is generated, if I can't figure out verlog or VHDL's
logic I refuse to write in it. Why do we not have a good logic language
(RTL?) for hardware? ( I consider them to be COBOL of the digital world).
> In my case, I haven’t reached that point yet. My models currently
> only run in simulation (GHDL to be specific).
I have FPGA board here, so I use Crash and burn testing.
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