PDP-12 at the RICM
ggs at shiresoft.com
Wed Jul 15 00:15:08 CDT 2015
On 7/14/15 9:53 PM, Fred Cisin wrote:
>>>> The 8086 had four segment registers:
>>>> CS - Code segment, used with IP register
>>>> DS - Data segment
>>>> SS - Stack segment, used with SP and BP registers
>>>> ES - Extra segment, used with DI for string instructions as
>>>> destination (DS:SI as source)
>>>> You could override instructions dealing with memory with any of the
>>>> segment registers:
>>> If you were writing an emulator, what would you have it do if an
>>> interrupt occurred while in a REP operation with a segment override?
>>> Just how accurately should an emulator match the behavior of the
>>> emulated processor?
> On Tue, 14 Jul 2015, Guy Sotomayor wrote:
>> It's actually described in the Intel SDM (Software Developer's
>> Manual). ;-)
>> The start of the instruction is actually the segment override (one of
>> the things that makes decoding x86 instructions hard). Since the REP
>> XXX instructions are interruptible, the IP does not move to the next
>> instruction until after it completes (and the state of the REP XXX
>> instruction is kept in various registers that are updated on each
>> So, when an interrupt occurs, the execution is stopped (after the
>> iteration completes) and is restarted when the interrupt returns.
> That certainly sounds reasonable, but,
> have you noticed the difference in behavior of 8086/8088 V 80386?
Haven't. The SDM covers Pentium forward (and even then it attempts to
document the differences between the different models). I think
anything prior to
that has been relegated to "incompatible" prior products if their
different from what is described.
The 8086/8088 were done in a similar vein to the 8080 and 8008. Not too
much attention was paid to forward looking architectural decisions. The
and follow on CPUs *tried* to look forward a bit but it wasn't really
the Pentium when features such as the TSC and APIC were introduced.
TTFN - Guy
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