Differences between the PDP-11/15 and PDP-11/20
jnc at mercury.lcs.mit.edu
Tue Aug 23 13:05:32 CDT 2016
> From: Paul Popelka
> I was wondering how much delay the KT-11B introduces.
That's a _very_ interesting question; AFAIK, the documentation doesn't say.
If there's a cache miss, of course, there's one memory cycle delay to load
If the cache hits, though, there's still added gate delays going through the
KT11 - perhaps 20-30 or so (to make a complete guess) - at ~10nsec each, that
would be an extra 200 nsec per memory cycle. Not insignificant...
> There is still the actual implementation of the KA11 changes that can
> be reverse engineered if someone is so inclined.
Well, that might not be trivial - if the boards have ECOs, it may be hard to
tell them from the KT11 changes. The sheet which gives the wiring changes for
the KA11 backplane _is_ still there - although there are indications on it
that the actual machine differs from the prints! Wheee! :-(
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