Transporting an LGP-30
paulkoning at comcast.net
Fri Dec 30 11:49:36 CST 2016
> On Dec 30, 2016, at 12:51 AM, Jon Elson <elson at pico-systems.com> wrote:
> On 12/29/2016 10:04 PM, Noel Chiappa wrote:
> Ouch! That means it runs one instruction per revolution of the drum? that would slow it to something like 30 IPS!
>> Oh, I think a good case can be made. People often cite the LINC as the first,
>> but the G-15 and LGP-30 were similar in cost and intent, albeit a generation
>> (at least) older.
> SEVERAL generations older. Core memory was a HUGE advance. Rather more complicated than a drum, but got rid of the horrid latency with a drum. Even if you optimized the executable code, machines like the G-15 had all sorts of insane trickery to make data access faster. There were instructions that would copy a whole long line of data to the short lines so that these could be accessed every 4 word times, instead of having to wait a full drum revolution for the next word.
The Dutch computer ARMAC had a nice optimization, a track buffer. Under software control a given track would be copied to that buffer (in some sort of RAM -- core?) and then references to those addresses would be satisfied from the buffer. You could think of that as a very early cache. That was the machine on which Dijkstra first implemented the spanning tree algorithm (as a demo program for an exhibition).
For first generation machines, you could distinguish between vacuum tube ones, and the earlier relay machines.
I have an old set of lecture notes I'm translating, for a course on computer design from 1948, which discusses various memory types. Not core memory, that came later. But it mentions drums, and theorizes that those might be operated at 60,000 rpm... I'm not sure where that optimism came from. Perhaps because the author was a mathematician rather than a mechanical engineer?
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