Another MEM11 Status update
ggs at shiresoft.com
Sun Feb 28 01:15:53 CST 2016
I've been simulating parts of the MEM11 FPGA since the last time I sent
out an update.
Most of my time has been writing various testcases and getting them to
work on Xilinx's
I'm making pretty good progress and have tested a fair number of the
modules in the
MEM11 FPGA design. I have found some bugs in my code but most of the
actually been in my test cases.
So far I've tested (and they "work"):
* Various "register" modules that I've written
* Reset sequencer
* Status jumpers and status LEDs
* LED panel interface for the RF11 LEDs
* FRAM interface
* absolute and periodic timers
* Hardware multiplier
* DMA FIFO
These all form the high level blocks that the J1 micro will interface
to. My test code is
actually using the registers and register addresses (MMIOs) that the J1
The next blocks to test are the UART interface and all of the various
aspects of the
UNIBUS interface (which I've partitioned into about 6 distinct modules
each of which
will be tested separately).
I'm still undecided with the UART as to how far to go in creating a
for the UART part itself (vs just making something that has the
of registers and can "wiggle" the interrupt line). I did create a
behavioral model for
the FRAMs but that was relatively easy (just some big arrays).
Once I have the UNIBUS tested out, I'll figure out how to get the J1 to
test code and I'll re-run all of the tests on the full FPGA design with
tests on the J1.
I'm pretty excited as I'm not finding a lot of issues with the design.
UNIBUS modules may have more issues due to the relative complexity of
on there. Plus the test cases will be much more involved (ie I have to
write tests to
not only initialize the various aspects of the UNIBUS module but also
UNIBUS transactions with correct timing). However, I'm getting better
the testcases and what I usually run into now are typo's.
TTFN - Guy
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