CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?
paulkoning at comcast.net
Mon Jun 20 20:15:06 CDT 2016
> On Jun 20, 2016, at 5:12 PM, ben <bfranchuk at jetnet.ab.ca> wrote:
> On 6/20/2016 2:41 PM, Toby Thain wrote:
>> This is frankly amazing. Thankyou for the details. Maybe one day I'll be
>> able to volunteer some help. (Actually if there's anything I can do now,
>> as an electronics noob but beginning student of digital logic & FPGA,
>> let me know offlist.)
> How about a REAL FPGA board that has 5 volt I/O and 36+ bit wide memory
> would make some big computers a reality.
Given the right level of internal detail, a PDP10 emulation should be straightforward.
Just to give you a feeling for the currently available scale, I figured that a large but not max size FPGA can hold a complete CDC 6600 -- its 15 chassis worth of modules, including PPU and CPU memory. The only thing that -- probably -- doesn't quite fit is the ECS. But CPU memory, 128k words of 60 bits, is perfectly straightforward inside a modern large FPGA. (Good thing, too; the CM timing is such that trying to hook up external RAM is quite a pain, unless you make it SRAM. ECS is far more lenient.)
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