CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?
bfranchuk at jetnet.ab.ca
Mon Jun 20 23:07:01 CDT 2016
On 6/20/2016 9:43 PM, Eric Smith wrote:
> On Mon, Jun 20, 2016 at 9:34 PM, ben <bfranchuk at jetnet.ab.ca> wrote:
>> My other pet-peave is that every thing is point and click wizard for any
>> useful modules. Need a rom module or adder module, point and click no
>> portable code.
> I predominantly use Xilinx, and I don't use much point-and-click at
> all. I do all my HDL editing in emacs, including instantiating any of
> the Xilinx-provided IP blocks. My main interaction with the Xilinx
> software (whether ISE or Vivado) is to click the "generate bitstream"
> button. It's even possible to do that from the command line or a
> Makefile, but I haven't bothered.
Do you use Static or Dynamic ram with the FPGA's?
More information about the cctech