CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

Paul Koning paulkoning at
Tue Jun 21 10:35:27 CDT 2016

> On Jun 21, 2016, at 11:24 AM, Chuck Guzis <cclist at> wrote:
> On 06/21/2016 07:25 AM, Paul Koning wrote:
>>> On Jun 20, 2016, at 11:53 PM, Chuck Guzis <cclist at>
>>> wrote:
>>> Are you going for the 6600 CPU with PPU or just the CPU itself?
>> The whole thing.  The intent is to be able to run code, and you need
>> PPUs for that.  Besides, part of the motivation was to understand
>> esoteric details of how PPUs work.  The PPUs are actually
>> straightforward; I have those running.  The CPU is trickier, and of
>> course much larger.
> I take it that your PPs use the "one ALU, ten memories" model of the
> 6600 and not the independent PPUs of the 7600 and 180?

Correct, because my model is a gate level transcription of the original design.  I'm NOT building this model from the system functional specification, but rather from the actual module schematics and wire lists.

> Will your 6600 have an option for ECS?

That's the intent.  This is tricky because I have not seen wire lists for the ECS coupler.  I should be able to do without the ECS controller (modeling ECS functionally at that interface point).  But the ECS coupler contains details that the CPU hooks into, and also some semi-unrelated details like central/monitor exchange jump processing.

There are block diagrams, and those will have to serve if all else fails, but that means reverse engineering the module level detail (or, more precisely, constructing a functionally equivalent set of module level details).  I keep hoping that some day the missing details will be found.  Similarly, there are some other details that are missing; the PPU wire lists predate the central/monitor exchange jump feature so that too would have to be reconstructed from less detailed information.


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