dkelvey at hotmail.com
Sun May 29 09:24:04 CDT 2016
DRam is technically no slower to read than static. It is the house
keeping functions that cost time. Typically the floating nets are
designed to hold data for over 2 milliseconds. At todays higher
speed processors, the refresh time is hardly noticed.
As for the processors of this time, the primary concern was cost.
Not so much silicon size but yield. Bigger ICs had lower yields,
raising cost. Today yields are much better.
Also, in the days of the 6502, complementary CMOS was not only
expensive, it was slow. Making extra logic and gates required more
power as every data inversion required a pull up resistance in single
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Mike Ross <tmfdmike at gmail.com>
Sent: Sunday, May 29, 2016 2:13:07 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Monster 6502
On May 29, 2016 2:44 PM, "Noel Chiappa" <jnc at mercury.lcs.mit.edu> wrote:
> > From: drlegendre
> > Gawd, what a lovely piece of work that man hath wrought!
> I love the term he invented for it: "dis-integrated circuit"! :-)
> Good FAQ page here:
> My favourite entry:
> "Q: Are you nuts?
> A: Probably."
> Clearly a person after our own hearts! :-)
I'm sure I read of someone who was implementing an entire CPU as discrete
components on an even larger size... there were racks of the thing; it took
up most of a room.
But I can't find the link....
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