Meaning of "architecture width" - Re: 68K Macs with MacOS 7.5 still in production use...
Guy Sotomayor Jr
ggs at shiresoft.com
Fri Sep 16 19:04:23 CDT 2016
> On Sep 16, 2016, at 4:41 PM, Chuck Guzis <cclist at sydex.com> wrote:
> On 09/16/2016 03:20 PM, Jecel Assumpcao Jr. wrote:
>> Note that in the conclusion to this 1979 article, the Motorola
>> engineers say "It is a 32-bit architecture that supports many data
>> types and data addresses."
The important part (I believe) is to differentiate “architecture” from
“implementation”. It is quite possible to have a single architecture
with multiple implementations. For example, the IBM 360. It is a
32-bit architecture. It had a number of implementations where the
data paths were 8, 16 and 32 bits. Does that mean that the models
that were implemented with 8 bit data paths were an 8 bit architecture
and the models with 16 bit data paths were 16 bit architecture?
I think not.
Where some confusion comes in when we call something a 32-bit
machine. Does that refer to its architecture or its implementation?
> Unfortunately, that doesn't clear the picture any.
Sure it does. It say “architecture” in the above quote, so I think that
> What would you call a Packard-Bell PB250, with its bit-serial ALU and
> delay line memory? It had a 22 bit word, with addressing granularity to
> match. So it's a 22-bit architecture?
What is the programming model? If the 22 bit word is the fundamental
unit of expression (ie registers and memory are fundamentally organized
around 22-bits) then I would say it’s a 22-bit architecture.
> The TMS9900 has already been identified as a 16-bit ISA, even with its
> bit-serial ALU.
> So some enterprising soul could device a shift-register-based MPU with
> 1-bit memory bus, but with a 256 bit word size and it would be a 256 bit
It’s very similar to the AVX instructions on Intel. The latest are 512-bit
instructions. Some *implementations* have 256 bit data paths. But no
one argues that the AVX instruction architecture is 512-bits.
Likewise, using memory width as a differentiator is also un-informative
(as well as being “just an implementation detail”). For example, IBM’s
POWER processors have had 256 and 512 bit data bussesfor many years
(basically the width was determined by the size of a cache line). Would
that make them 256/512 bit architectures?
The latest Intel CPUs also have very wide paths to memory (some of
which is determined by how many banks of DRAM are installed).
TTFN - Guy
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