Meaning of "architecture width" - Re: 68K Macs with MacOS 7.5 still in production use...
spectre at floodgap.com
Fri Sep 16 21:33:45 CDT 2016
> > I don't think this follows. Looking at the TMS 9900 datasheet, the
> > block diagram shows a full 16 bits on each ALU input and 16 bits
> > leaving it. There's no 1-bit bus directly to memory.
> So the "bitedness" is determined by the memory bus? e.g., a 68008 is an
> 8-bit MPU?
I'm not sure where we're missing each other here, but by pointing out the
TMS 9900 had a bit-serial ALU, the implication (?) was that it was chewing
through things one bit at a time. However, internally, it presents a full
16 bits to each ALU input and pulls off a full 16 bits from the output --
it's not going out to memory and grabbing a bit per ALU machine cycle.
> The PB250 is serial throughout--the registers are implemented as 1 bit
> recirculating devices that are 22 bits in length. Memory is addressable
> in 22 bit words (no shorter unit of addressing is present) and is again,
> loops of recirculating serial data. Basic operations are performed on
> 22-bit words. FWIW, it's a one-plus-one instruction set.
So why wouldn't this be a 22-bit architecture?
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