2.11BSD on two RL02 drives? Probably not, but...

Guy Sotomayor Jr ggs at shiresoft.com
Fri Aug 4 15:31:09 CDT 2017


> On Aug 4, 2017, at 1:20 PM, Paul Koning via cctalk <cctalk at classiccmp.org> wrote:
> 
> 
>> On Aug 4, 2017, at 3:46 PM, Noel Chiappa via cctalk <cctalk at classiccmp.org> wrote:
>> 
>>> From: David Bridgham dab at froghouse.org 
>> 
>>> I'm going to have enough fun with trying to implement the USB stack in
>>> the FPGA
>> 
>> ISTR discussing putting a PDP-11 into the FPGA (there are Verilog PDP-11's
>> available), so we could write our USB code in C (I'd use the Unix V6 compiler
>> to compile it, of course :-).
> 
> That's a possibility.  I've thought about using a rough approximation of a CDC 6000 series PPU for this sort of stuff, since it's a nice small instruction set (and I have the VHDL for it already...)  A more likely answer would be to find a working Forth FPGA model and use that.
> 

One already exists: J1.  It’s *tiny* @ ~300 lines of Verilog.  Everything (including all of the J1’s memory) easily fits in a Spartan 3E FPGA (I don’t recall what percentage it uses).  I’m using it in UMF11 (Unibus Multi-function) board that I’m doing.  The J1 plus all of the other stuff for the UMF11 fits in the FPGA without too much fuss.

I’ve written a full simulator for the J1 (version 1 is in Forth natch), so it’s much easier to debug than poking in the FPGA.  I’m working on version 2 (written in C) which allows more flexibility in dealing with simulating various I/O.

TTFN - Guy



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