early (pre-1971) edge-triggered D flip-flop ICs

Brent Hilpert bhilpert at shaw.ca
Wed Jul 19 18:40:52 CDT 2017


On 2017-Jul-19, at 3:10 PM, Eric Smith via cctalk wrote:
> I'm interested in the history of the logic design for the edge-triggered D
> flip-flop, as used in the SN7474. The design is composed of three set-reset
> latches (six NAND gates total) per flip-flop.
> 
> Does anyone know what year the SN7474 was introduced, or have an early
> datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st
> Edition?
> 
> The earliest datasheet I've found using this specific logic design for an
> edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola
> MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The
> MC3060 is covered in the Motorola 1968 IC databook, on page 4-138.
> 
> I've searched US patents for edge-triggered flip-flop design, but have not
> found one specifically for the three S-R latch design.
> 
> The subject came up as a result of a discussion on a private mailing list
> regarding the fact that the conventional J-K master-slave flip-flop design
> is NOT edge-triggered; pulses on J and/or K while the clock is high but
> stable can affect the Q (and not-Q) outputs of the FF at the following
> falling edge of the clock. That behavior is known as "pulse catching", and
> such a flip-flop is properly called pulse-triggered or level-triggered, but
> not edge-triggered.  Early datasheets on J-K master-slave flip-flops
> actually had correct terminology and specifically stated that J and K
> should not change while the clock is high.


The 1969 TI TTL IC Catalog presents slightly more info about the 7474, compared to the minimal table-oriented presentation of the 73 databook.
Extract;
		Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time
		of the positive going pulse. After the clock input threshold voltage has been passed, the data input (D) is locked out.

		These dual flip-flops have the same clocking characteristics of the SN5470/SN7470 gated (edge-triggerred) flip-flop circuits, . . .

A transistor level schematic is present as well.

The internal operation of the 7474 is discussed in the Sams book "TTL" by George Flynn / 1974.
A decent page+ of text , but I haven't read it in depth so don't really know how good an explanation it is.
Cursorily, it seems to be just a logic explanation that anyone could figure out by working through the logic diagram,
not an electrical level explanation.

There are near-type cross-refs in the 69 book to the National DM8510, Sprague NE8828, Sprague USN7474, and Signetics N7474.

I can take and email you photos of the applicable pages if you like.
Don't have a web site up right now to put them up on.



More information about the cctech mailing list