early (pre-1971) edge-triggered D flip-flop ICs

Paul Koning paulkoning at comcast.net
Fri Jul 21 09:25:53 CDT 2017


> On Jul 21, 2017, at 10:12 AM, Vincent Slyngstad via cctalk <cctalk at classiccmp.org> wrote:
> 
> From: Ethan Dicks: Thursday, July 20, 2017 11:08 AM
>> On Thu, Jul 20, 2017 at 11:35 AM, Norman Jaffe via cctech
>> <cctech at classiccmp.org> wrote:
>>> Or, in today's dollars - $58. Ouch.
>> Wow!  That's many dollars per flip and or flop!
> 
> If that lasted any time at all, one can see the rationale behind things like DEC's Posibus/Negibus (in which fantastic amounts of cabling that costs $$$ today are expended to save a gate or two).

The economies of different parts of a design clearly change over the years.  Now you can add thousands of transistors at zero cost, it's just a microscopic added amount of space on a large chip.  But when each transistor was a separate component that had to be built, packaged, purchased, and soldered into place, things were a bit different.  Bob Supnik described it well with his "economy of gates" note a few months ago.

Wires vs. circuitry is one obvious example.  We use high speed serial buses now because logic is cheap.  In decades past, lots of wires were used because wires and connectors were cheaper than transistors -- and also because the space taken up by those wires wasn't the predominant issue compared to the space taken up by logic.  I remember being amazed when DEC's SDI disk interconnect came out (in the RA80).  I didn't understand then what was going on: the transition from "save logic, add wires" to "we can afford to use logic to cut it down to just a few wires".

	paul



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