Kryoflux or Catweasle

Al Kossow aek at
Wed May 24 16:28:19 CDT 2017

On 5/24/17 12:58 PM, ben via cctalk wrote:

> With typo in VHDL you have hard problem finding that single gate
> error.

The world has been debugging 100,000+ gate systems with simulations for
a few decades now.

Once you've built up a set of test vectors, it actually becomes really
obvious where a single gate error is through simulation.

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