Kryoflux or Catweasle

Jecel Assumpcao Jr. jecel at
Wed May 24 17:29:59 CDT 2017

Al Kossow wrote on: Wed, 24 May 2017 14:28:19 -0700
> On 5/24/17 12:58 PM, ben via cctalk wrote:
> > With typo in VHDL you have hard problem finding that single gate
> > error.
> The world has been debugging 100,000+ gate systems with simulations for
> a few decades now.
> Once you've built up a set of test vectors, it actually becomes really
> obvious where a single gate error is through simulation.

In addition, a tool like the Altera Signal probe allows you to bring any
signal you want to a pin you select so you can use an oscilloscope or
logic analizer to look at it if that is how you are more comfortable
debugging hardware. Another option is to include a whole logic analyzer
inside your design, like the Xilinx ChipScope or Altera SignalTap II.
That talks to software running on your PC and has all the functionality
of a real logic analyzer.

I have not used these tools myself but instead did the equivalent the
hard way: I patched the VHDL code to bring the signal I wanted to look
at to the pin I was probing with my oscilloscope. That was a bit awkward
when the signal was several levels down in the design.

My point is that though Al is right that it is better to debug with a
simulator, those of us who prefer to look at the real thing lose nothing
with FPGAs. In fact, given how hard it can be to attatch 60 little
probes to pins which are very close together we actually gain something.

By the way, in my scheme I actually had a case where it was hard to
debug because the FPGA worked one way when I touched it with the
oscilloscope probe and did something different when I didn't.

-- Jecel

More information about the cctech mailing list