Kryoflux or Catweasle
paulkoning at comcast.net
Thu May 25 10:39:53 CDT 2017
> On May 25, 2017, at 11:35 AM, Jon Elson via cctalk <cctalk at classiccmp.org> wrote:
> On 05/24/2017 02:58 PM, ben via cctalk wrote:
>> I am not to sure about that.
>> If a schematic has a bug you can use a logic probe to find the error.
>> With typo in VHDL you have hard problem finding that single gate
> With Xilinx, they have a VERY good simulator. You create a "test bench" in VHDL or other HDL to describe external signals.
You can do the same with other VHDL processors. If you don't want to deal with a particular manufacturer and potentially pay major money for the tool set, there's GHDL, a open source GCC-based VHDL modeler. It has some handy capabilities, such as a way to hook C functions into the model.
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