Core memory emulator using non volatile ram.

Charles Anthony at
Sat Dec 15 20:32:19 CST 2018

On Sat, Dec 15, 2018 at 6:15 PM Rod G8DGR via cctalk <cctalk at>

> All very interesting.. 1201 alarm while I deal will all of the information
> Rod

1202 coming up...

I don't know specifically about the various memory types being bandied
about, but I do know that the destructive read behavior of core memory my
be required for some architectures; "load and clear" type instructions rely
on the suppressing the write-after-read cycle to make the instruction
atomic, allowing the implementation of data locking instructions. For some
architectures,  it may be that any replacement memory would have to support
the suppression signal to work correctly.

-- Charles

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