Core memory emulator using non volatile ram.
jnc at mercury.lcs.mit.edu
Mon Dec 17 12:52:36 CST 2018
> From: Paul Koning
> For that matter, core memory details such as destructive read weren't
> visible to the CPU
Umm, not quite. If you'd said 'core memory details such as destructive read
weren't visible to the _program_', you'd have been 100% correct.
But as I suspect you know, just overlooked, most (all?) of the -11 CPU's do
use 'read-modify-write' cycles on the bus (DATIP in UNIBUS terms, DATIO in
QBUS) where possible precisely for the benefit of core memory with its
destructive readout. (And there's some hair for interlocking the multiple
CPU's on the -11/74 which I don't recall off the top of my head.)
And I have a vague memory of something similar on other early DEC machines;
probably some -8 models.
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