Another DCJ11 oddity
jsw at ieee.org
Tue Jul 10 07:58:39 CDT 2018
On 7/10/18 5:01 AM, Noel Chiappa via cctalk wrote:
> So, if one looks up the Cache Control Register in, say, the KDJ11-A
> (EK-KDJ1A-UG-002), one sees (in section 184.108.40.206) that there are _three_ ways
> to disable the cache: bits 2, 3 ('force miss'), and 9 ('bypass cache').
> Looking at the DCJ11 manual (EK-DCJ11-UG-PRE) doesn't provide any additional
> (The 9 bit one is slightly different than the other two, because it causes
> cache contents to be invalidated as the code runs, whereas the other two
> What is going on here, does anyone know? I'm _guessing_ that this is for
> compatability with the -11/70, where the cache is divided in two ('two-way set
> associative'), and either half can be disabled separately (using the 2 and
> 3 bits in its CCR).
> I suppose only someone who worked on the DCJ11 would know; but I have no idea
> how to track down such a person.
See http://simh.trailing-edge.com/semi/j11.html for information on the
design of the J11. This may give you the 11/70 background you are seeking.
I've always assumed the differences in controls in the CCR as necessary
to support diagnostics of memory and the cache itself.
In addition to above, there is a bypass cache bit in the PDR (section
220.127.116.11) for finer control. This will help support memory mapped
devices which update those memories independently. Lastly there is a
selective bypass for certain instructions related to multiprocessing.
EK-DCJ11-UG-PRE Section 5.2.4 describes three bypass mechanisms.
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