PDP-11/45 RSTS/E boot problem
paulkoning at comcast.net
Wed Feb 6 19:29:29 CST 2019
> On Feb 6, 2019, at 8:25 PM, Brent Hilpert via cctalk <cctalk at classiccmp.org> wrote:
> On 2019-Feb-06, at 5:11 PM, Fritz Mueller via cctalk wrote:
>>>> On Feb 6, 2019, at 2:24 PM, Brent Hilpert via cctalk <cctalk at classiccmp.org> wrote:
>>>> Is the schematic available for the memory board at-issue?
>>>> Curious myself to see what approach for refresh DEC used.
>>> Yes, here: http://bitsavers.trailing-edge.com/pdf/dec/pdp11/memory/MP00672_MS11L_engDrw.pdf
>> For completeness, from the technical manual:
>> "The refresh logic, shown in sheet 6 of the print set, generates REF CLK H and the refresh address. Sig- nal REF CLK H is derived from a 555 timer (E5) which is set up as a free running oscillator, powered by the + IS V / + 12 V module input (V-555). The REF CLK H signal oscillates with a period of 14.5us and has a positive pulse width of 6us during each period."
> So I could have saved myself some fun if I had read the manual rather than just looking at the schematic.
> Not that they're way out of whack, but the mild disparity between the manual's 14.5uS and my calculated 11.7uS is curious
> (the calculation being based on the schematic RC values and the 555 equations).
Perhaps the period was changed in a schematic rev or ECO, and the manual wasn't updated to reflect it. It would be interesting to check the data sheet for the RAM chip to see what it likes for refresh cycle. And given that this is an RC oscillator your theory about out of tolerance timing definitely deserves checking.
More information about the cctech