PDP-11/45 RSTS/E boot problem

Brent Hilpert bhilpert at shaw.ca
Thu Feb 7 01:06:53 CST 2019

On 2019-Feb-06, at 10:37 PM, Fritz Mueller via cctalk wrote:

>> 4116 datasheet specs 2mS, my calcs give a refresh period of 1.5mS, the 14.5uS from the manual would give 1.86 mS, 7% shy of 2.
>> The schematic specs 1% resistors, and the parts list does appear to spec a high-tolerance "1%200PPM" cap.
>> Although there are the internal voltage divider Rs in the 555 which are also critical for the timing and everything is 40+ years old.
>> Idle speculation at my distance, we'll see what Fritz observes.
> Brent:  11.8us, 6.4us position 
> Manual: 14.5us, 6.0us positive
> Actual: 15.2us, 8.5us positive
> So yeah, a little pokey there...

15.2uS gives a 1.95mS refresh, so it's awfully close to the 2mS spec, but still within.
The datasheet I was looking at doesn't seem to give any spec for tolerance on the refresh so one would guess there's a safety margin built into the 2mS spec.

Seems a little less-likely to be the problem, given(?) as well that you have fairly consistent (is deterministic overstating it?) behaviour.

If you wanted to test it by experiment, without having to remove the installed Rs, you could test-clip another R in parallel with the 38.4K,
probably something around 200K, to shorten the 555 period.

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