plated wire memory
dkelvey at hotmail.com
Mon Oct 21 10:08:33 CDT 2019
The plated wire sounds like really fussy stuff. The layer of permalloy had to be thin but not to thin. I suspect that was to optimize the internal field compared to the outside word select signal.
At first, I couldn't understand why they'd need to use beryllium copper but it seems the wires needed to be free standing in the array. Pure copper would sage and touch.
Clearly an interesting process. If it had not been for solid state, I suspect it would have been refined to a more manufacturable process. I suspect tuning the layer thickness could have been done while in the plating bath instead of waiting until it was outside.
Because of the size of things, I suspect it could have been done by vapor deposit on glass substrates and miniaturized. It depended on the fact that the field had a preferred direction and couldn't be easily rotated. Such things can be done on a flat surface with current day processing.
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Chuck Guzis via cctalk <cctalk at classiccmp.org>
Sent: Sunday, October 20, 2019 2:23 PM
To: dwight via cctalk <cctalk at classiccmp.org>
Subject: Re: plated wire memory
On 10/20/19 1:50 PM, dwight via cctalk wrote:
> It is funny that the most common memory used today is a DRO type memory. The read destroys much of the charge on a DRAM cell, requiring a write back of the data.
That's true today, but probably not in the near future. Persistent
memory is getting faster and cheaper.
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