Looking for an IDE simulator
dab at froghouse.org
Fri Aug 28 14:49:51 CDT 2020
On 8/28/20 3:31 PM, Warner Losh wrote:
> There's some other speed increase (UHS) that comes along with also
> dropping from 3.3V down to 1.8V. I don't know how to program
> FPGAs to
> do that or even know if they can.
> I thought it was going from SPI mode to MMC mode that did this, not
> the double clocking nor the 1bit to 4bit bus steps.
I knew it wasn't either the double clocking or using all four lanes, I
just didn't know what it was called and was too lazy to dig out the SD
But now I pulled up the spec and it's saying that it's UHS cards that
support the modes that use the lower voltage and there are seven bus
DS (Default Speed)
HS (High Speed)
DS and HS use 3.3V signaling while the SDR and DDR modes use 1.8V. Then
UHS-II adds a couple more modes. SPI mode is separate from all of this,
something just tossed in there for us hobbyists to play around with.
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