Modifying a RXV21 for an 11/83
jsw at ieee.org
Sun Jan 24 20:51:55 CST 2021
On 1/24/21 8:11 PM, Chris Zach wrote:
> Ok. My guess is it throws off the cache on the 11/73 and above as it
> works in an 11/23 (which is soooooo slow!).
> I looked at the images, cut the traces, then soldered in two of the
> wires. Board did not work on either the 11/83 or the 11/23+ CPU.
> However when I looked closer I saw the tiny little wire down by the
> crystal and the Q bus fingers. Put that in, and the board now works on
> the 11/23+, will take the whole thing apart (again) and plug in the
> Fortunately I have the pdp11/83 configured with a Q bus memory board
> (2-4mb) and a PMI memory board from an 11/84 placed in slot 2 (so the
> 11/83 will access it as Q Bus memory). Thus I could pull the 11/83 CPU
> in slot 1 and pop the 11/23+ in. Aside from the exceptionally slower
> speed and long boot times it works pretty well for testing.
> Still need to get a 11/83 compatible PMI board, but the 11/84 ones
> work as normal Q bus memory.
> Thanks! Now I can read some of these RX02 disks and image them. I'm
> guessing my BRU floppy that I generated with the RXV11 controller will
> not boot on this RXV21 controller so I'll have to re-make that. And so
> far it doesn't look like the disks made on that third party MXV21
> controller are compatible with the RX02, should they be?
Most of the third party controllers and drives are OS compatible with
the RX01 + RX02 format, provided you stick with Single Sided media.
However, booting an OS with an RX01 controller handler (Interrupt
driven) will not succeed with an RX02 controller (DMA) or vice-versa.
The Double Sided media (RX03) make for interesting interchange stories.
I've seen double sided single density floppies. There are also
differences in how the controller vendors made disk handler
modifications for RT11. Many of these controllers would allow you to
perform a low level format, but only using vendor specific controller
commands. The DEC RX02 will only change the funky media density.
Remember that these are 18 bit controllers. Some operation systems can
work around this limitation, at the expense of CPU cycles.
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