8 Aug
2025
8 Aug
'25
10:21 a.m.
On Aug 8, 2025, at 12:54 PM, Maciej W. Rozycki
<macro(a)orcam.me.uk> wrote:
On Thu, 7 Aug 2025, Paul Koning wrote:
All of those (except for the precise opcode field widths) go back to the CDC 6600, which
though not often called that clearly deserves to be seen as an early, probably the first,
RISC architecture.
paul
>>> ...
The key concepts clearly borrowed from the MIPS ISA were: a hardwired
zero register and the dependency on that for the completeness of the ALU
operations provided, the lack of condition codes and the use of general
registers instead for conditional branches, and the overall feel of the
instruction set, including but not limited to the 6-bit major opcode
encoded in bits 31:26 of the instruction word and the placement of the
5-bit register operand fields.