[cctalk] Re: Good C to FPGA/PLA compiler

On Sep 23, 2023, at 5:06 PM, Will Cooke via cctalk <cctalk(a)classiccmp.org> wrote: I can't answer for Paul, but I can tell you how to do approximate calculations for yourself. You need to know two things: the equivalent parallel resistance (Thevenin equivalent) of the two series resistors and the input capacitance of the driven pin (including stray capacitance.) If you assume the input+stray capacitance is 10 pF (a reasonable first approximation) and the resistance is 1000 Ohms, the time constant (time for the signal to go from 0 to 63% of max) will be 1000 * 10E(-12) seconds or 10,000 picoseconds = 10 nanoseconds. That assumes the 5V output can switch instantaneously into the 5 mA or so load. I would double that for the real world. So the signal gets delayed around 20 nS and the output has to drive 5 mA or so. A more realistic divider might be 5K or 10K resistance for less power consumption and less strain on the output. With 10K you are looking at a delay of 100 to 200 nS. If the timing isn't critical you "might" be able to go as high as 5 MHz that way. But probably more like 1 MHz is more realistic. I've used voltage divider level translation at about 1 MHz, using something like 2200 and 4700 ohms for the divider (Thevenin equivalent 1500.)