[cctalk] Re: 80386 - 1985

SIMD micro architectures use conditional execution at the mill (or pair of mills for complex operands) level. This removes the program sequencer and global condition codes from consideration, only the mill's "local condition" controls arithmetic operation. The technique appeared in ~2nd generation DSP chips in the late 80's and became common when they embraced multi core / multi mill architectures, I presume it has the merit of not "breaking" the pipelining. It can now be found in R and A series Arm cores. I imagine there are anteceedents prior to its use in the DSP 56300 and Sharc processors. The ordinal instruction is IFcc, where the specific operation and cc are also specified in the instruction encoding and conditional execution is local to each mill (or pair). Martin -----Original Message----- From: Paul Koning via cctalk [mailto:cctalk@classiccmp.org] Sent: 08 August 2025 17:52 To: cctalk(a)classiccmp.org Cc: Paul Koning <paulkoning(a)comcast.net> Subject: [cctalk] Re: 80386 - 1985 The same thing as branch on register? Nope, "skip on condition" is a flavor of condition code branch. The RISC argument against condition codes, and why Cray didn't use them in the 6600, is that they are an instruction side effect that has to be interlocked along with the "real" result. And it's a global state, so it introduces unwanted serialization. For example, in a 6600 (or a MIPS or an Alpha), you can have an add into R3 executing concurrently with a multiply into R4, with no output conflicts. If you add condition codes to the architecture, those are a second output and the two operations now conflict. Another advantage is that you can conditionally branch on a result from some number of instructions ago, while instructions in between are still finishing up. No need to drain the pipeline. Of course there are other ways to do the "some instructions ago" thing, by having condition codes that are set only if an instruction option says to do so. The Electrologica machines (X1, from 1958, and the successor X8) have that feature, making them similar to ARM but more flexible. The 6600 max memory was 128k 60-bit words, which for those days was admittedly quite large. No VM, though it did support relocation (base address and field length, similar to the DEC KA10). Large RAM is nice but I don't see what it has to do with RISC. paul